1. Field of the Invention
The present invention relates to a semiconductor memory circuit with an improved memory cell structure.
2. Description of the Prior Art
A conventional dual-port Random Access Memory (RAM), having an exclusive port for a reading operation and another for a writing operation, and a memory cell thereof are shown in FIGS. 2 and 1, respectively.
As shown in FIG. 1, a dual-port memory cell 53 has a pair of word lines AW and BW, a first pair of data lines AD and ADB and a second pair of data lines BD and BDB. A single-bit memory cell 53 is deposited at an intersection of the lines AW, BW, AD, ADB, BD and BDB.
The memory cell 53 contains a pair of inverters 38 and 39 for data latching, and four N-channel MOS transistors 11, 12, 13 and 14 as gate elements for controlling data input and output operations to the latch.
The input end of the inverter 38 and the output end of the inverter 39 are connected in common to a connection point 40 and the input end of the inverter 39 and the output end of the inverter 38 are connected in common to a connection point 41, which constitute a well-known data latch circuit.
The gate element 11 is placed between the connection point 40 and the data line AD. The word line AW is connected to the control terminal of the gate element 11. The gate element 13 is placed between the connection point 40 and the data line BD. The word line BW is connected to the control terminal of the gate element 13.
The gate element 12 is placed between the connection point 41 and the data line ADB. The word line AW is connected to the control terminal of the gate element 12. The gate element 14 is placed between the connection point 41 and the data line BDB. The word line BW is connected to the control terminal of the gate element 14.
The entire architecture of the conventional dual-port RAM is shown in FIG. 2. In this RAM, N.sub.x memory cells 53 are arranged horizontally and N.sub.y memory cells 53 are arranged vertically, resulting in an N.sub.x .times.N.sub.y matrix array 200 of the cells 53. First to nth matrix arrays 200 of the memory cells 53 are aligned horizontally. Therefore, this RAM can store information of n bits x (N.sub.x .times.N.sub.y) words.
First to nth data input/output sections 201 are provided for the respective memory cell arrays 200. Each of the data input/output sections 201 contains a column selector 54, a data-writing section 55 and a data-reading section 56.
A row decoder 51 receives an address signal and generates a row select signal to output it to the respective memory cell arrays 200. The row to be read out or to be written in is selected by the row select signal during a reading or writing operation.
A column decoder 52 receives the address signal and generates a column select signal to output it to the respective column selectors 54 and the respective data-writing sections 55 of the data input/output sections 201. One of the columns to be read out or to be written in is selected by the column select signal during a reading or writing operation.
In a write operation, the data-writing section 55 receives a data value to be stored and sends it to the memory cells 53 contained in the selected column.
In a read operation, the column selector 54 receives the data stored in the memory cells 53 of the row selected to be read out, and selects one of the columns containing desired data therefrom according to the column select signal.
The data reading section 56 outputs the data received from column selector 54.
The data lines AD of all the memory cells 53 contained in each column of the memory cell matrix 200 are connected in common and the data lines ADB thereof are connected in common. Similarly, the data lines BD of all the memory cells 53 contained in each column of the memory cell matrix 200 are connected in common and the data lines BDB thereof are connected in common.
The word lines AW of all the memory cells 53 contained in each row of the memory cell matrix 200 are connected in common and the word lines BW thereof are connected in common.
The row select signal outputted from the row decoder 51 is inputted to the common-connected word lines AW and BW of all the memory cells 53, respectively.
The output of the data-writing section 55 is inputted to the common-connected data lines AD and ADB of all the memory cells 53 and to the common-connected data lines BD and BDB thereof, respectively.
The outputs of the memory cells 53 are inputted to the column-selector 54 through the common-connected data lines AD and ADB and through the common-connected data lines BD and BDB, respectively.
During a write operation, for example, when the word line AW of the memory cell 53 selected is driven to a high logic state 1, then the gate elements 11 and 12 close. The data value to be stored is transferred to the data lines AD, ADB BD and BDB of the selected memory cell 53 through the data writing section 55, respectively.
Next, the first pair of the data lines AD and ADB are driven to opposite logic states, respectively. That is, the data line AD is a high logic state 1 and the data line ADB is a low logic state 0, or the data line ADB is a high logic state 1 and the data line AD is a low logic state 0. In the former case, the data is stored in the inverter 38 through the gate element 11. In the latter case, the data is stored in the inverter 39 through the gate element 12.
During a read operation, for example, he word line AW of a selected memory cell 53 is driven to a low logic state 0, and the data lines AD and ADB are precharged to high logic states 1, respectively.
Next, the word line AW is changed to a high logic state 1 to close gate elements 11 and 12, and then either of the data lines AD and ADB is changed to a low logic state 0 according to the stored data value in the inverter 38 or 39.
This change in logic state of the data line AD or ADB is transferred through the column selector 54 to the data-reading section 56 to be read out.
The precharge of the data lines AD and ADB during a read operation is carried out to avoid false data writing. If the precharge step is not performed, when the word line AW is changed to a high logic state 1 under the condition that one of the data lines AD and ADB is in a high logic state 1 and the other is a false low logic state 0, a data (transferred through data line AD or ADB) is erroneously stored.
Write and read operations for the other word line BW and the other data lines BD and BDB are similar to the operations described above.
The conventional dual-port RAM has the following problems:
First, when a given data value is stored in the conventional RAM, it is stored in just one of the N.sub.x .times.N.sub.y memory cells 53 arranged in the matrix array 200, but the other cells 53 thereof must maintain their data values.
However, with the N.sub.x memory cells 53 contained in one row selected by the row decoder 51, as described above, the word line AW or BW of the same selected row is driven to a high logic state 1 during a write operation. Therefore, to prevent the given data value from being stored in the memory cells 53 contained in the columns not selected by the column decoder 52, the same operation as the read operation is required during a write operation.
In detail, for example, the word line AW or BW of the selected memory cell 53 is driven to a low logic state 0, and the pair of the data lines AD and ADB or the pair of the data lines BD and BDB are precharged to high logic states 1, respectively. Thereafter, the word line AW or BW is changed to a high logic state 1 to close gate elements 11 and 12, or gate elements 13 and 14, respectively and then either of the pair of the data lines AD and ADB or the pair of the data lines BD and BDB is changed to a low logic state 0 due to the data value stored in inverter 38 or 39. During this period of time, the given data to be stored is transferred to the memory cell 53 selected by the row decoder 51 and the column decoder 52 to be stored therein.
Accordingly, even if only one of the N.sub.x pairs of the data lines AD and ADB or those of the data lines BD and BDB is sued for the write operation, read operations are required for the remaining (N.sub.x -1) pairs thereof, respectively. As a result, the power dissipation for these remaining pairs is wasted.
Second, when a single data value stored in the conventional RAM is read out, the desired data value stored in a selected one of the N.sub.x .times.N.sub.y memory cells 53 is sufficient to be read out and the data values stored in the remaining cells 53 are not required to be read out.
However, with the N.sub.x memory cells 53 contained in one row selected by the row decoder 51, as described above, the word line AW or BW of the same selected row is driven to a high logic state 1 during a read operation. Therefore, the remaining memory cells 53 not selected by the column decoder 52 are subjected to the read operations.
In detail, for example, the word line AW or BW of the selected memory cell 53 is driven to a low logic state 0, and the N.sub.x pairs of the data lines AD and ADB or the N.sub.x pairs of the data lines BD and BDB are precharged to high logic states 1, respectively. Thereafter, the word line AW or BW is changed to a high logic state 1 to close gate elements 11 and 12 or gate elements 13 and 14, respectively and then either of the pair of the data lines AD and ADB or the pair of the data lines BD and BDB is changed to a low logic state 0 according to the data value stored in inverter 38 or 39.
Accordingly, even if only one of the N.sub.x pairs of the data lines AD and ADB or those of the data lines BD and BDB is used for the read operation, the same read operations are required for the remaining (N.sub.x -1) pairs thereof, respectively. As a result, the power dissipation for these remaining pairs is wasted.